Waveform Transition Graphs: a designer-friendly formalism for asynchronous behaviours

The paper proposes a new formal model for describing asynchronous behaviours involving the interplay of causality, concurrency and choice. The model is called Waveform Transition Graphs. Its main aim is simplifying the learning process for industrial engineers in accessing powerful synthesis tools provided for Signal Transition Graphs by sacrificing some of the expressive power of the latter. This formalism is developed based on feedback from engineers of Dialog Semiconductor.Peer ReviewedPostprint (author's final draft

Logic design of asynchronous circuits

Summary form only given. This tutorial aims at motivating the audience to consider asynchronous circuits as a competitive alternative to solve some of the design problems inherent to submicron technologies. One of the main reasons why designers are reluctant to incorporate asynchrony in their systems is the difficulty to design asynchronous circuits. Asynchronous circuits are promising to tackle problems such as electro-magnetic interference, power consumption, performance, and modularity of digital circuits. The tutorial will introduce state-of-the-art tools and methodologies for their design. It will cover aspects such as specification, architectural design and controller synthesis tools, of asynchronous circuits. The tutorial will concentrate on a particular design methodology for control circuits based on specifications with signal transition graphs. It will also cover design strategies for the microarchitecture, data-path and control circuits that have been successfully applied in the design of the asynchronous version of the ARM microprocessor.Peer ReviewedPostprint (published version

Automatic synthesis and optimization of partially specified asynchronous systems

A method for automating the synthesis of asynchronous control circuits from high level (CSP-like) and/or partial STG (involving only functionally critical events) specifications is presented. The method solves two key subtasks in this new, more flexible, design flow: handshake expansion, i.e. inserting reset events with maximum concurrency, and event reshuffling under interface and concurrency constraints, by means of concurrency reduction. In doing so, the algorithm optimizes the circuit both for size and performance. Experimental results show a significant increase in the solution space explored when compared to existing CSP-based or STG-based synthesis tools.Peer ReviewedPostprint (author's final draft

Slimming down Petri Boxes: Compact Petri Net Models of Control Flows

We look at the construction of compact Petri net models corresponding to process algebra expressions supporting sequential, choice, and parallel compositions. If "silent" transitions are disallowed, a construction based on Cartesian product is traditionally used to construct places in the target Petri net, resulting in an exponential explosion in the net size. We demonstrate that this exponential explosion can be avoided, by developing a link between this construction problem and the problem of finding an edge clique cover of a graph that is guaranteed to be complement-reducible (i.e., a cograph). It turns out that the exponential number of places created by the Cartesian product construction can be reduced down to polynomial (quadratic) even in the worst case, and to logarithmic in the best (non-degraded) case. As these results affect the "core" modelling techniques based on Petri nets, eliminating a source of an exponential explosion, we hope they will have applications in Petri net modelling and translations of various formalisms to Petri nets

What is the cost of delay insensitivity?

Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behaviour. Asynchronous speed-independent (SI) circuits, whose behaviour is only robust to gate delay variations, may be too optimistic. On the other hand, building circuits totally delay-insensitive (DI), for both gates and wires, is impractical. The paper presents an approach for automated synthesis of globally DI and locally SI circuits. It is based on order relaxation, a simple graphical transformation of a circuit's behavioural specification, for which the Signal Transition Graph, an interpreted Petri net, is used. The method is successfully tested on a set of benchmarks and a realistic design example. It proves effective showing average cost of DI interfacing at about 40% for area and 20% for speed.Peer ReviewedPostprint (published version

Serialized Asynchronous Links for NoC

This paper proposes an asynchronous serialized link for NoC that can achieve the same levels of performance in terms of flits per second as a synchronous link but with a reduced number of wires in the point to point switch links and reduced power consumption. This is achieved by employing serialization in the asynchronous domain as opposed to synchronous to facilitate the removal of global clocking on the serial links. Based on transistor level simulations using 0.12 ?m foundry models it has been shown that it is possible to achieve the same level of performance as synchronous but with 75% reduction in wires and 65% reduction in power for a 300 MFlit/s link with 8 buffers with a switch clock speed of 300 MHz. Furthermore the paper presents the design requirements arising from interfacing switches of synchronous NoC and asynchronous serial links

Neural network design of multilayer metamaterial for temporal differentiation

Controlling wave-matter interactions with metamaterials (MTMs) for the calculation of mathematical operations has become an important paradigm for analogue computing given their ability to dramatically increase computational processing speeds. Here, motivated by the importance of performing mathematical operations on temporal signals, we propose, design and study multilayer MTMs with the ability to calculate the derivative of incident modulated temporal signals, as an example of a significant computing process for signal processing. To do this, we make use of a neural network (NN) based algorithm to design the multilayer structures (alternating layers of indium tin oxide (ITO) and titanium dioxide (TiO2)) that can calculate the first temporal derivative of the envelope of an impinging electromagnetic signal at telecom wavelengths (modulated wavelength of 1550 nm). Different designs are presented using multiple incident temporal signals including a modulated Gaussian as well as modulated arbitrary functions, demonstrating an excellent agreement between the predicted results (NN results) and the theoretical (ideal) values. It is shown how, for all the designs, the proposed NN-based algorithm can complete its search of design space for the layer thicknesses of the multilayer MTM after just a few seconds, with a low mean square error in the order of (or below) 10^-4 when comparing the predicted results with the theoretical spectrum of the ideal temporal derivative.Comment: 4 Figures, 17 page

Deriving Petri nets from finite transition systems

This paper presents a novel method to derive a Petri net from any specification model that can be mapped into a state-based representation with arcs labeled with symbols from an alphabet of events (a Transition System, TS). The method is based on the theory of regions for Elementary Transition Systems (ETS). Previous work has shown that, for any ETS, there exists a Petri Net with minimum transition count (one transition for each label) with a reachability graph isomorphic to the original Transition System. Our method extends and implements that theory by using the following three mechanisms that provide a framework for synthesis of safe Petri nets from arbitrary TSs. First, the requirement of isomorphism is relaxed to bisimulation of TSs, thus extending the class of synthesizable TSs to a new class called Excitation-Closed Transition Systems (ECTS). Second, for the first time, we propose a method of PN synthesis for an arbitrary TS based on mapping a TS event into a set of transition labels in a PN. Third, the notion of irredundant region set is exploited, to minimize the number of places in the net without affecting its behavior. The synthesis method can derive different classes of place-irredundant Petri Nets (e.g., pure, free choice, unique choice) from the same TS, depending on the constraints imposed on the synthesis algorithm. This method has been implemented and applied in different frameworks. The results obtained from the experiments have demonstrated the wide applicability of the method.Peer ReviewedPostprint (published version